Dr. Otilia Boaghe – OPTIM-ACEMP

Plenary Session Speakers

Dr. Otilia Boaghe

Dr. Otilia Boaghe (Ing, MRes, PhD) received a degree in electrical engineering in 1995 from Transilvania University of Brasov, Romania, and the Ph.D. (2000) from University of Sheffield, UK.

The topic of her dissertation is the analysis of the strongly non-linear systems.

She is currently Staff Engineer at ARM Ltd in Cambridge, UK (since 2019). Her 20+ years industry experience involves ASICs design and verification, at Philips Semiconductors, NXP, Texas Instruments (subcontractor) and Synopsys (subcontractor). She designed several IP’s for the last generation multimedia processors, and applied verification tools and methodologies in the DPU verification of ARM processors.

Dr Boaghe collaborated with Transilvania University of Brasov during 2012 – 2019 delivering “Testing of Integrated Circuits”, a 4th year course at the Dept. of Electronics and Computers Engineering. Her research interests include: embedded systems architectures for low-power electronics applications, machine-learning, artificial intelligence.

Verification of RISC processors – challenges with innovative solutions

Abstract

The need for a fast, reusable and robust verification methodology is acknowledged across several processor families in industry. A configurable and extensible test-bench is now the standard approach in verification of complex RISC processors. This presentation is going to summarize the state of the art in verification techniques and methodologies used in industry for these very complex digital systems. The challenges imposed by the increasing complexity and ever shorter time-to-market requirements are the prerequisites in finding efficient and flexible solutions, resulting in test-benches which may compete in performance and complexity with the processors under test themselves. The tools and methodologies employed in processor verification are required to provide high reliability and fast results. The verification methods used need to optimize code and functional coverage metrics and are tested against a high-level model to find device incorrectnesses during the generation time. The verification flow itself needs to be compact yet efficient. This presentation will bring several examples from the most efficient and popular RISC processors used today in industry.